1实现思路
有5个数a,b,c,d,e
将其分为3组,ab, cd, e
e留到最后再比较,
先比较ab 和 cd
设得出了ab的较小值 a a < b
设得出了cd的较小值 c c < d
第一个分支
比较ac, 设a < c
那么 a < c < d , a < b
将b,e比较 ,
1,b< e
a < c < d
a < b < e
接着对c和b比较,
c<b,则 a<c<b<e,
再比较b、d,若b<d,b是中位数,若b>d,d是中位数
若b<c,则a<b<c<d,
再比较c、e,若c<e,c是中位数,若c>e,e是中位数
2,b>e
a<c<d
a<b,e<b
比较e,c,若e<c
比较b,c,若b<c,b是中位数,否则c是中位数
若e>c,
比较d,e,若d<e,d是中位数,否则是中位数
第2个分支
若 a > c
则按照上面的步骤推即可。
verilog实现
module sort5(input clk,input rst_n,input [7:0] data1,input [7:0] data2,input [7:0] data3,input [7:0] data4,input [7:0] data5,output reg [7:0] max_data,output reg [7:0] mid_data,output reg [7:0] min_data
);//-----------第一步-----------
reg [7:0] min_d12;
reg [7:0] max_d12;
//对 data1 和data2 比较
always@(posedge clk or negedge rst_n)beginif(!rst_n) beginmin_d12 <= 8'd0;max_d12 <= 8'd0;endelse if(data2 < data1) beginmin_d12 <= data2;max_d12 <= data1;endelse beginmin_d12 <= data1;max_d12 <= data2;end
endreg [7:0] min_d34;
reg [7:0] max_d34;
//对 data3 和data4 比较
always@(posedge clk or negedge rst_n)beginif(!rst_n) beginmin_d34 <= 8'd0;max_d34 <= 8'd0;endelse if(data3 < data4) begin min_d34 <= data3;max_d34 <= data4;endelse beginmin_d34 <= data4;max_d34 <= data3;end
end//-----------第2步-----------
reg [7:0] data5_reg;
always@(posedge clk or negedge rst_n)beginif(!rst_n) data5_reg <= 8'd0; else data5_reg <= data5;
endreg [7:0] min_data; //求最小值
always@(posedge clk or negedge rst_n)beginif(!rst_n) beginmin_data <= 8'd0; endelse if(min_d34 < min_d12) beginif(min_d34 < data5_reg)min_data <= min_d34; else min_data <= data5_reg; endelse beginif(min_d12 < data5_reg)min_data <= min_d12; else min_data <= data5_reg; end
endreg [7:0] max_data; //求最大值
always@(posedge clk or negedge rst_n)beginif(!rst_n) beginmax_data <= 8'd0; endelse if(max_d34 < max_d12) beginif(max_d12 < data5_reg)max_data <= data5_reg; else max_data <= max_d12; endelse beginif(max_d34 < data5_reg)max_data <= data5_reg; else max_data <= max_d34; end
end//得到5个数的中值
always@(posedge clk or negedge rst_n)beginif(!rst_n) beginmid_data<= 8'd0;endelse if(min_d12 < min_d34) begin if(max_d12 < data5_reg) begin if(min_d34 < max_d12) if(max_d12 < data5_reg)mid_data <= max_d12;else mid_data <= data5_reg;else if(max_d34 < data5_reg)mid_data <= max_d34;else mid_data <= data5_reg;endelse beginif(data5_reg < min_d34) if(max_d12 < min_d34)mid_data <= max_d12;else mid_data <= min_d34;else if(max_d34 < data5_reg)mid_data <= max_d34;else mid_data <= data5_reg;endendelse beginif(max_d34 < data5_reg) begin if(min_d12 < max_d12) if(max_d34 < data5_reg)mid_data <= max_d34;else mid_data <= data5_reg;else if(max_d12 < data5_reg)mid_data <= max_d12;else mid_data <= data5_reg;endelse beginif(data5_reg < min_d12) if(max_d34 < min_d12)mid_data <= max_d34;else mid_data <= min_d12;else if(max_d12 < data5_reg)mid_data <= max_d12;else mid_data <= data5_reg;end end
end