基于FPGA的VGA协议实现

文章目录

一、VGA介绍
- 1.VGA协议
- 2.VGA端口
- 3.色彩原理
二、屏幕上显示彩色条纹
- 1.创建工程
- 2.代码编写
- 3.实现效果
三、显示自定义的汉字字符
- 1.字模提取
- 2.代码
四、输出一幅彩色图像
- 1.转图片格式
- 2.调用IP核
- 3.结果
五、总结

一、VGA介绍

1.VGA协议

什么是VGA？VGA不是用来显示的那块屏幕，而是用来传输信号的接口。VGA全称是Video Graphics Array，即视频图形阵列，是模拟信号的一种视频传输标准。不⽀持热插拔，不⽀持⾳频传输。对于⼀些嵌⼊式VGA显示系统，可以在不使⽤VGA显卡和计算机的情况下，实现VGA图像的显示和控制。VGA显示器具有成本低、结构简单、应⽤灵活的优点。

2.VGA端口

VGA端口是视频输出端口，端口一共包含15个管脚，如下图
在这里插入图片描述

VGA接口是一种D型接口，上面共有15针孔，分成三排，每排五个。其中，除了2根NC（Not Connect)信号、3根显示数据总线和5个GND信号，比较重要的是3根RGB彩色分量信号和2根扫描同步信号HSYNC和VSYNC针。VGA接口中彩色分量采用RS343电平标准。RS343电平标准的峰值电压为1V。VGA接口是显卡上应用最为广泛的接口类型，多数的显卡都带有此种接口。有些不带VGA接口而带有DVI(Digital Visual Interface数字视频接口）接口的显卡，也可以通过一个简单的转接头将DVI接口转成VGA接口，通常没有VGA接口的显卡会附赠这样的转接头。

在通常使用的连接方法里面，15个管脚里面的5个是最重要的，他们包括3个基本红、绿、蓝三条基本色彩和水平与垂直两条控制线。
在这里插入图片描述
大多数计算机与外部显示设备之间都是通过模拟VGA接口连接，计算机内部以数字方式生成的显示图像信息，被显卡中的数字/模拟转换器转变为R、G、B三原色信号和行、场同步信号，信号通过电缆传输到显示设备中。对于模拟显示设备，如模拟CRT显示器，信号被直接送到相应的处理电路，驱动控制显像管生成图像。而对于LCD、DLP等数字显示设备，显示设备中需配置相应的A/D（模拟/数字）转换器，将模拟信号转变为数字信号。在经过D/A和A/D两次转换后，不可避免地造成了一些图像细节的损失。VGA接口应用于CRT显示器无可厚非，但用于连接液晶之类的显示设备，则转换过程的图像损失会使显示效果略微下降。
而且可以从接口处来判断显卡是独显还是集成显卡，VGA接口竖置的说明是集成显卡，VGA接口横置说明是独立显卡（一般的台式主机都可以用此方法来查看）。

3.色彩原理

三基⾊是指通过其他颜⾊的混合⽆法得到的“基本⾊”由于⼈的⾁眼有感知红、绿、蓝三种不同颜⾊的锥体细胞，因此⾊彩空间通常可以由三种基本⾊来表达

设计RGB信号时，既可以R信号、G信号和B信号独⽴的赋值，最后连到端⼝上，也可以直接⽤RGB当做⼀个整体信号，RGB信号在使⽤时的位宽有三种常见格式，以你的VGA解码芯⽚的配置有关。
RGB_8，R：G：B = 3：3：2，即RGB332
RGB_16，R：G：B = 5：6：5，即RGB565
RGB_24，R：G：B = 8：8：8，即RGB888
依次对应8、16、24位位宽，位宽越高，图像越清晰

二、屏幕上显示彩色条纹

1.创建工程

通过python脚本创建好工程文件夹，然后进行代码编写

2.代码编写

在这里插入图片描述
上图verilog文件定义了会使用的一些变量
在vga_ctrl中则是控制vga显示的逻辑
代码：

`define vga_800_600
`include "vga_param.v"
module vga_ctrl (input                clk       ,input                rst_n     ,input        [23:0]  data_dis  ,output  reg  [10:0]  h_addr    ,   //数据有效显示区域行地址output  reg  [10:0]  v_addr    ,   //数据有效显示区域场地址output  reg          hsync     ,output  reg          vsync     ,output  reg  [7:0]   vga_r     ,output  reg  [7:0]   vga_g     ,output  reg  [7:0]   vga_b     ,output  reg          vga_blk   ,   //VGA消隐信号output  reg          vga_clk     
);//参数定义parameter H_SYNC_STA = 1 ,H_SYNC_STO = `H_Sync_Time ,H_DATA_STA = `H_Sync_Time + `H_Back_Porch + `H_Left_Border ,H_DATA_STO = `H_Sync_Time + `H_Back_Porch + `H_Left_Border + `H_Data_Time ,V_SYNC_STA = 1 ,V_SYNC_STO = `V_Sync_Time ,V_DATA_STA = `V_Sync_Time + `V_Back_Porch + `V_Top_Border ,V_DATA_STO = `V_Sync_Time + `V_Back_Porch + `V_Top_Border + `V_Data_Time;//信号定义reg     [11:0]      cnt_h_addr     ;  //行地址计数器wire                add_cnt_h_addr ;wire                end_cnt_h_addr ;reg     [11:0]      cnt_v_addr     ;  //场地址计数器wire                add_cnt_v_addr ;wire                end_cnt_v_addr ;always @(posedge clk or negedge rst_n) beginif(!rst_n)begincnt_h_addr <= 1'd0;endelse if(add_cnt_h_addr)beginif(end_cnt_h_addr)begincnt_h_addr <= 1'd0;endelse begincnt_h_addr <= cnt_h_addr + 1'd1 ;endendendassign add_cnt_h_addr = 1'd1 ;assign end_cnt_h_addr = add_cnt_h_addr && cnt_h_addr == `H_Total_Time - 1 ;always @(posedge clk or negedge rst_n) beginif(!rst_n)begincnt_v_addr <= 1'd0;endelse if(add_cnt_v_addr)beginif(end_cnt_v_addr)begincnt_v_addr <= 1'd0;endelse begincnt_v_addr <= cnt_v_addr + 1'd1;endendendassign add_cnt_v_addr = end_cnt_h_addr;assign end_cnt_v_addr = add_cnt_v_addr && cnt_v_addr == `V_Total_Time - 1 ;//行场同步信号always @(posedge clk or negedge rst_n) beginif(!rst_n)beginhsync <= 1'b1;endelse if(cnt_h_addr == H_SYNC_STA - 1)beginhsync <= 1'b0;endelse if(cnt_h_addr == H_SYNC_STO - 1)beginhsync <= 1'b1;endendalways @(posedge clk or negedge rst_n) beginif(!rst_n)beginvsync <= 1'b1;endelse if(cnt_v_addr == V_SYNC_STA - 1)beginvsync <= 1'b0;endelse if(cnt_v_addr == V_SYNC_STO - 1)beginvsync <= 1'b1;endendalways @(posedge clk or negedge rst_n) beginif(!rst_n)beginvga_clk <= 1'b1;endelse beginvga_clk <= ~vga_clk;endend//assign vga_clk = ~clk ;always @(posedge clk or negedge rst_n) beginif(!rst_n)beginh_addr <= 11'b0;endelse if((cnt_h_addr >= H_DATA_STA - 1) &&(cnt_h_addr <= H_DATA_STO - 1))beginh_addr <= cnt_h_addr - H_DATA_STA;endelse beginh_addr <= 11'd0;endendalways @(posedge clk or negedge rst_n) beginif(!rst_n)beginv_addr <= 11'b0;endelse if((cnt_v_addr >= V_DATA_STA - 1) && (cnt_v_addr <= V_DATA_STO - 1))beginv_addr <= cnt_v_addr - V_DATA_STA;endelse beginv_addr <= 11'd0;endendalways @(posedge clk or negedge rst_n) beginif(!rst_n)beginvga_r <= 8'd0;vga_g <= 8'd0;vga_b <= 8'd0;vga_blk <= 1'b0;endelse if((cnt_h_addr >= H_DATA_STA - 1) && (cnt_h_addr <= H_DATA_STO - 1) && (cnt_v_addr >= V_DATA_STA - 1) && (cnt_v_addr <= V_DATA_STO - 1)) beginvga_r <= data_dis[23:16];vga_g <= data_dis[15:8] ;vga_b <= data_dis[7:0]  ;vga_blk <= 1'b1         ;endelse beginvga_r <= 8'd0;vga_g <= 8'd0;vga_b <= 8'd0;vga_blk <= 1'b0;endendendmodule

data_gen则是vga显示的数据生成文件
代码：

module data_gen (input                clk       ,input                rst_n     ,input        [10:0]  h_addr    ,   //数据有效显示区域行地址input        [10:0]  v_addr    ,   //数据有效显示区域场地址output  reg  [23:0]  data_dis  
);//参数定义parameter BLACK   = 24'h000_000 ,RED     = 24'hFF0_000 ,GREEN   = 24'h00F_F00 ,BLUE    = 24'h000_0FF ,YELLOW  = 24'hFFF_F00 ,SKY_BULE= 24'h00F_FFF ,PURPLE  = 24'hFF0_0FF ,GRAY    = 24'hC0C_0C0 ,WHITE   = 24'hFFF_FFF ;always @(posedge clk or negedge rst_n) beginif(!rst_n)begindata_dis <= WHITE;endelse begincase (h_addr)0  : data_dis <= BLACK   ;100 : data_dis <= RED     ;200: data_dis <= GREEN   ;300: data_dis <= BLUE    ;400: data_dis <= YELLOW  ;500: data_dis <= SKY_BULE;600: data_dis <= PURPLE  ;700: data_dis <= GRAY    ;default:data_dis<=data_dis; endcaseendendendmodule

顶层文件：

module vga_top (input                 clk       ,input                 rst_n     ,output  wire          hsync     ,output  wire          vsync     ,output  wire  [7:0]   vga_r     ,output  wire  [7:0]   vga_g     ,output  wire  [7:0]   vga_b     ,output  wire          vga_blk   ,output  wire          vga_clk  
);wire     [23:0]   data_dis  ;wire     [10:0]   h_addr    ;wire     [10:0]   v_addr    ;data_gen u_data_gen(.clk       (clk     )  ,.rst_n     (rst_n   )  ,.h_addr    (h_addr  )  ,   //数据有效显示区域行地址.v_addr    (v_addr  )  ,   //数据有效显示区域场地址.data_dis  (data_dis)  
);vga_ctrl u_vga_ctrl(.clk        (clk     ) ,.rst_n      (rst_n   ) ,.data_dis   (data_dis) ,.h_addr     (h_addr  ) ,   //数据有效显示区域行地址.v_addr     (v_addr  ) ,   //数据有效显示区域场地址.hsync      (hsync   ) ,.vsync      (vsync   ) ,.vga_r      (vga_r   ) ,.vga_g      (vga_g   ) ,.vga_b      (vga_b   ) ,.vga_blk    (vga_blk ) ,.vga_clk    (vga_clk )  
);endmodule

3.实现效果

在这里插入图片描述

三、显示自定义的汉字字符

1.字模提取

在PCtoLCD上取字模
在这里插入图片描述
取出字模数据

2.代码

module VGA_test(
OSC_50,     //原CLK2_50时钟信号
VGA_CLK,    //VGA自时钟
VGA_HS,     //行同步信号
VGA_VS,     //场同步信号
VGA_BLANK,  //复合空白信号控制信号  当BLANK为低电平时模拟视频输出消隐电平，此时从R9~R0,G9~G0,B9~B0输入的所有数据被忽略
VGA_SYNC,   //符合同步控制信号      行时序和场时序都要产生同步脉冲
VGA_R,      //VGA绿色
VGA_B,      //VGA蓝色
VGA_G);     //VGA绿色input OSC_50;     //外部时钟信号CLK2_50output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;output [7:0] VGA_R,VGA_B,VGA_G;parameter H_FRONT = 16;     //行同步前沿信号周期长parameter H_SYNC = 96;      //行同步信号周期长parameter H_BACK = 48;      //行同步后沿信号周期长parameter H_ACT = 640;      //行显示周期长parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;        //行空白信号总周期长parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;  //行总周期长耗时parameter V_FRONT = 11;     //场同步前沿信号周期长parameter V_SYNC = 2;       //场同步信号周期长parameter V_BACK = 31;      //场同步后沿信号周期长parameter V_ACT = 480;      //场显示周期长parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;        //场空白信号总周期长parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;  //场总周期长耗时reg [10:0] H_Cont;        //行周期计数器reg [10:0] V_Cont;        //场周期计数器wire [7:0] VGA_R;         //VGA红色控制线wire [7:0] VGA_G;         //VGA绿色控制线wire [7:0] VGA_B;         //VGA蓝色控制线reg VGA_HS;reg VGA_VS;reg [10:0] X;             //当前行第几个像素点reg [10:0] Y;             //当前场第几行reg CLK_25;always@(posedge OSC_50)begin CLK_25=~CLK_25;         //时钟end assign VGA_SYNC = 1'b0;   //同步信号低电平assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK));  //当行计数器小于行空白总长或场计数器小于场空白总长时，空白信号低电平assign VGA_CLK = ~CLK_to_DAC;  //VGA时钟等于CLK_25取反assign CLK_to_DAC = CLK_25;always@(posedge CLK_to_DAC)beginif(H_Cont<H_TOTAL)           //如果行计数器小于行总时长H_Cont<=H_Cont+1'b1;      //行计数器+1else H_Cont<=0;              //否则行计数器清零if(H_Cont==H_FRONT-1)        //如果行计数器等于行前沿空白时间-1VGA_HS<=1'b0;             //行同步信号置0if(H_Cont==H_FRONT+H_SYNC-1) //如果行计数器等于行前沿+行同步-1VGA_HS<=1'b1;             //行同步信号置1if(H_Cont>=H_BLANK)          //如果行计数器大于等于行空白总时长X<=H_Cont-H_BLANK;        //X等于行计数器-行空白总时长   （X为当前行第几个像素点）else X<=0;                   //否则X为0endalways@(posedge VGA_HS)beginif(V_Cont<V_TOTAL)           //如果场计数器小于行总时长V_Cont<=V_Cont+1'b1;      //场计数器+1else V_Cont<=0;              //否则场计数器清零if(V_Cont==V_FRONT-1)       //如果场计数器等于场前沿空白时间-1VGA_VS<=1'b0;             //场同步信号置0if(V_Cont==V_FRONT+V_SYNC-1) //如果场计数器等于行前沿+场同步-1VGA_VS<=1'b1;             //场同步信号置1if(V_Cont>=V_BLANK)          //如果场计数器大于等于场空白总时长Y<=V_Cont-V_BLANK;        //Y等于场计数器-场空白总时长    （Y为当前场第几行）  else Y<=0;                   //否则Y为0endreg valid_yr;always@(posedge CLK_to_DAC)if(V_Cont == 10'd32)         //场计数器=32时valid_yr<=1'b1;           //行输入激活else if(V_Cont==10'd512)     //场计数器=512时valid_yr<=1'b0;           //行输入冻结wire valid_y=valid_yr;       //连线   reg valid_r;            always@(posedge CLK_to_DAC)   if((H_Cont == 10'd32)&&valid_y)     //行计数器=32时valid_r<=1'b1;                   //像素输入激活else if((H_Cont==10'd512)&&valid_y) //行计数器=512时 valid_r<=1'b0;                   //像素输入冻结wire valid = valid_r;               //连线wire[10:0] x_dis;     //像素显示控制信号wire[10:0] y_dis;     //行显示控制信号assign x_dis=X;       //连线Xassign y_dis=Y;       //连线Yparameter  //点阵字模：每一行char_lineXX是显示的一行，共304列char_line00=256'h0000000000000000000000000000000000000000000000000000000000000000,  //第1行char_line01=256'h0000000000000000000000000000000000000000000000000000000000000000,  //第2行char_line02=256'h0001000000800200000020000000000000000000000000000000000000000000,  //第3行char_line03=256'h0001803000C0030000C070000000000000000000000000000000000000000000,  //第4行char_line04=256'h0C01002000C5030000E060000000000000000000000000000000000000000000,  //第5行char_line05=256'h071220203FFE86000180C0000000000000000000000000000000000000000000,  //第6行char_line06=256'h031FF02000C0D600018181000000000000000000000001E003C00FFC07E001E0,  //第7行char_line07=256'h0318302000C0D7FC018300C000000000000000000000061806200FFC08380618,  //第8行char_line08=256'h0018302000C8AC1803060060000000000000000000000C180C30100010180C18,  //第9行char_line09=256'h001830240FFC2A10031FFFF000000000000000000000081818181000200C0818,  //第10行char_line0a=256'h001FFFFC00002BA0060F003000000000000000000000180018181000200C1800,  //第11行char_line0b=256'h02183020100053000701001000000000000000000000100018081000300C1000,  //第12行char_line0c=256'h7F1830201FFF43000F018380000000000000000000001000300C1000300C1000,  //第13行char_line0d=256'h061830203007C2800B0300E0000000000000000000003000300C1000000C3000,  //第14行char_line0e=256'h061FF0203024C6801B0640700000000000000000000033E0300C13E0001833E0,  //第15行char_line0f=256'h061834206FF8C640130CE018000000000000000000003630300C143000183630,  //第16行char_line10=256'h061836200000CC402310C098000000000000000000003818300C181800303818,  //第17行char_line11=256'h061833200000C8604321FFC0000000000000000000003808300C100800603808,  //第18行char_line12=256'h061833200FF818300303018000000000000000000000300C300C000C00C0300C,  //第19行char_line13=256'h067FF3200C18201C0303018000000000000000000000300C300C000C0180300C,  //第20行char_line14=256'h0600F0200C18C0080304830000000000000000000000300C300C000C0300300C,  //第21行char_line15=256'h0601B0200FF906000308820000000000000000000000300C300C000C0200300C,  //第22行char_line16=256'h062130200C101B000310460000000000000000000000300C1808300C0404300C,  //第23行char_line17=256'h06C330200020191003202C0000000000000000000000180C1818300C0804180C,  //第24行char_line18=256'h0786302004309908030038000000000000000000000018081818201810041808,  //第25行char_line19=256'h070C30200230980C03001800000000000000000000000C180C302018200C0C18,  //第26行char_line1a=256'h061830200320984403007E00000000000000000000000E30062018303FF80E30,  //第27行char_line1b=256'h02203020024F98440300C7800000000000000000000003E003C007C03FF803E0,  //第28行char_line1c=256'h00C3E3E003F31870030301FC0000000000000000000000000000000000000000,  //第29行char_line1d=256'h0100E0E03E000FE0031C00700000000000000000000000000000000000000000,  //第30行char_line1e=256'h0000404030000000026000100000000000000000000000000000000000000000,  //第31行char_line1f=256'h0000000000000000000000000000000000000000000000000000000000000000;  //第32行reg[8:0] char_bit;always@(posedge CLK_to_DAC)if(X==10'd144)char_bit<=9'd272;   //当显示到144像素时准备开始输出图像数据else if(X>10'd144&&X<10'd416)     //左边距屏幕144像素到416像素时    416=144+272（图像宽度）char_bit<=char_bit-1'b1;       //倒着输出图像信息 reg[29:0] vga_rgb;                //定义颜色缓存always@(posedge CLK_to_DAC) if(X>10'd144&&X<10'd416)    //X控制图像的横向显示边界：左边距屏幕左边144像素  右边界距屏幕左边界416像素begin case(Y)            //Y控制图像的纵向显示边界：从距离屏幕顶部160像素开始显示第一行数据10'd160:if(char_line00[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;  //如果该行有数据 则颜色为红色else vga_rgb<=30'b0000000000_0000000000_0000000000;                      //否则为黑色10'd162:if(char_line01[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd163:if(char_line02[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd164:if(char_line03[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd165:if(char_line04[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000; 10'd166:if(char_line05[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd167:if(char_line06[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000; 10'd168:if(char_line07[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd169:if(char_line08[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000; 10'd170:if(char_line09[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd171:if(char_line0a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd172:if(char_line0b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd173:if(char_line0c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd174:if(char_line0d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd175:if(char_line0e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd176:if(char_line0f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd177:if(char_line10[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd178:if(char_line11[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd179:if(char_line12[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd180:if(char_line13[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd181:if(char_line14[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd182:if(char_line15[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd183:if(char_line16[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd184:if(char_line17[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd185:if(char_line18[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd186:if(char_line19[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd187:if(char_line1a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd188:if(char_line1b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd189:if(char_line1c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd190:if(char_line1d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd191:if(char_line1e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd192:if(char_line1f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;default:vga_rgb<=30'h0000000000;   //默认颜色黑色endcase endelse vga_rgb<=30'h000000000;             //否则黑色assign VGA_R=vga_rgb[23:16];assign VGA_G=vga_rgb[15:8];assign VGA_B=vga_rgb[7:0];
endmodule