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module top_module(input clk,input [7:0] in,input reset,    // Synchronous resetoutput [23:0] out_bytes,output done); //
parameter IDEL = 4'b0001,BYTE1 = 4'b0010,BYTE2 = 4'b0100,BYTE3 = 4'b1000;reg[3:0] state, next_state;reg[23:0] mid_vale = 24'd0;// FSM from fsm_ps2always @(posedge clk)beginif(reset)state <= IDEL;elsestate <= next_state;endalways@(*)begincase(state)IDEL:next_state = in[3]?  BYTE1:IDEL;BYTE1 : next_state = BYTE2 ;BYTE2 : next_state = BYTE3 ;BYTE3 : next_state = in[3]? BYTE1 : IDEL;default : next_state = IDEL;endcaseendalways@(posedge clk)beginif(reset)mid_vale <= 24'd0;else begincase(next_state)BYTE1 : mid_vale <= ((mid_vale << 8) | in);BYTE2 : mid_vale <= ((mid_vale << 8) | in);BYTE3 : mid_vale <= ((mid_vale << 8) | in);endcaseendendassign done = (state==BYTE3);assign out_bytes =  mid_vale ;
endmodule

此题数据输出值mid_vale 的赋值必须在时序逻辑下。写在组合逻辑下不通过。输出可以写在组合逻辑下。