采用读热码编写方式：
module top_module(input clk,input in,input areset,output out); ////reg [3:0]A = 4'd0001;// reg [3:0]B = 4'd0010;//reg [3:0]C = 4'd0100;// reg [3:0]D = 4'd1000;
//1、首先用读热码定义四个状态变量parameter A = 4'd0001 ,B = 4'd0010, C = 4'd0100,D = 4'd1000;
//2、定义两个状态（因为4个状态变量为4为所以这两个状态也应该定义为4位）reg [3:0]state,next_state;
//同步时序下的状态复位always@(posedge clk or posedge areset)beginif(areset)state <= A;else state <= next_state;end// 组合逻辑描述状态转移assign next_state[0] = (state[0]&& ~in) || (state[2]&& ~in);assign next_state[1] = (state[0]&& in) || (state[3]&& in )|| (state[1]&& in);assign next_state[2] = (state[1]&& ~in) || (state[3]&& ~in); assign next_state[3] = (state[2]&& in);//输出逻辑 assign out = (state[3] == 1);
endmodule二进制码 编写方式 ：
module top_module(input clk,input in,input areset,output out); ////1、定义两个状态reg [1:0] state,next_state;
//2、二进制码定义4个状态变量parameter A=0,B=1,C=2,D=3;// State flip-flops with asynchronous resetalways@(posedge clk or posedge areset)beginif(areset)state <= A;elsestate <= next_state;end// State transition logicalways@(*)begincase(state)A:next_state = in? B:A;B:next_state = in? B:C;C:next_state = in? D:A;D:next_state = in? B:C;endcaseend// Output logic//assign out = (state == D);always@(posedge clk or posedge areset)beginif(areset)out<= 0;else beginif(next_state == D)out <= 1;elseout <= 0;endendendmodule
注意定义A B C D为 parameter
