软件开发app开发定制外包33_西安市建设工程信息网诚信平台_好口碑的关键词优化_关键词seo排名

1 VCCO_MIO1

接1.8V

2 PS_MIO_VREF

接0.9V，可通过电阻分压

可通过电阻分压

3 PS的引脚

4 RXDLY TXDLY

RXDLY RXD[0]
TXDLY RXD[1]
与XC7Z020的PS端MAC连接，必须设置
RXDLY=1，TXDLY=1，其他设置组合网络均不能正常连接。

5 ZYNQ的MAC可以调整延时吗

参考：
https://adaptivesupport.amd.com/s/question/0D52E00006lLh56SAC/can-the-mac-controller-of-zynq7000-adjust-the-clock-and-data-delay?language=en_US

Q: can the mac controller of zynq7000 adjust the clock and data delay?
Using the mac controler of zynq7000 to directly connect to the mac of another arm through the RGMII interface, but the mac of the opposite arm requires 1.5ns delay for clk and data. Is the zynq7000’s mac side required for data and clock latency? Or can the delay be adjusted?

A: There is not tap delay or clock delay structure wtih GEM. We just meet timing with setup/hold values in the datasheet. It’s expected to be added by PHY or PCB trace.