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module test(
input   wire		clk							,
input wire btn,     // 按钮输入
output reg[1:0]	CMD		
);		reg btn_sync_1;       // 第一级同步寄存器
reg btn_sync_2;       // 第二级同步寄存器
reg btn_prev;         // 上一个时钟周期的按钮状态
reg state = 1;           // 同步按钮输入以避免亚稳态问题 https://blog.csdn.net/ResumeProject/article/details/144695677
always @(posedge clk) beginbtn_sync_1 <= btn;btn_sync_2 <= btn_sync_1;
end// 边沿检测逻辑
wire btn_pressed = ~btn_sync_2 && btn_prev;// 更新按钮的前一状态
always @(posedge clk) beginbtn_prev <= btn_sync_2;
end// 根据按钮按下更新状态
always @(posedge clk) beginif (btn_pressed) beginstate <= ~state; // 切换状态end
end// 驱动输出
always @(posedge clk) beginif(state)begin// 处理A状态事件end else begin// 处理~A状态事件end
end

按钮波形

           +----+|    |
-----------+    +--------------------------------- btn_sync_1+----+|    |
-------------+    +------------------------------- btn_sync_2+----+|    |
--------------+    +------------------------------ btn_prev++||
------------------++------------------------------ btn_pressed